SSM INSTITUTE OF ENGINEERING AND TECHNOLOGY
Sindalagundu
post, Dindigul – 624002
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
QUESTION BANK (ALL UNITS)
PART
-A
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1.
What is Dynamic Scheduling?
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2.
What is Speculation?
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3. What is Loop Level Parallelism.
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4. Define VLIW:-
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5. What is Loop Unrolling?
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6. Difference between Scalar and Vector Register?
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7. Define Chaining and Stribe.
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8. Define Flynn’s Classification.
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9. Explain the any two
Vector Instruction:-
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10.
Define Computer Architecture?
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11.
What is meant by Cache memory?
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12. State Amdahl’s law:-
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13. Define Response time and Throughput.
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14. Distinguish between Static and Dynamic Ram:-
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15. Difference between RISC and CISC?
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16. Define CPI-
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17. Define benchmarks.
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18. Explain dependability:-
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19.
Find the number of dies per 300 mm (30 cm) wafer for a die that is 1.5 cm on
a side and for a die that is 1.0 cm on a side
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20. What
are the five trends in Computer Technology?
21. How
to find the cost of Integrated circuits?
22. Give
an example for Data dependence.
23. What
is dependability?
24. List
the major advantages of dynamic scheduling using Tomosulo’s
25. What
is control hazard?
26. What
is meant by instruction level parallelism?
27. What
is meant by Branch penalty?
28. Differentiate
static prediction and dynamic prediction.
29.
Differentiate in-order and out-order execution
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30.
Differentiate GPU and CPU
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31. What are the
primary components of instruction set architecture of VMIPS?
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List the methods
for providing synchronization in threads
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32. Define
sequential consistency.
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33. Define
Symmetric Multiprocessor.
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34.
Differentiate Uniform and Non uniform memory access
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35. Suppose you
want to achieve a speedup of 80 with 100 processors. What fraction of the
original computation can be sequential?
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36. What is
Multiprocessor cache coherence?
37. What is
meant by false sharing?
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38. What is
meant by snooping?
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39. What is
meant by atomic exchange?
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40. What is
Multicore Architecture?
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41. What are the
advantages of DSM architecture?
42.
What is meant by reliability and availability?
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43. What is
similarities and differences between SCSI and IDE.
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44. List the six
basic optimizations techniques of cache.
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45. Types of
Storage Devices.
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46. Compare
Software and Hardware RAID
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47. What are the
advantages of CMP architectures?
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48. Why are
design issues of SMT and CMP architecture important?
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49. Write the
benefits of multi core Architecture.
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50. Explain the
need to implement Memory as a Hierarchy?
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What are the omissions in the SIMD
extension instruction set?
51. Draw
the basic structure of vector architecture.
52. What
is meant by SAXPY or DAXPY?
53. What
is meant by Loop carried dependencies?
54. What
is the use of vector mask register?
55. Draw
the basic structure of centralized shared memory multiprocessor
56. What
is meant by shared, uncached and modified states in snooping protocol?
57. What
is meant by sequential consistency?
58. List
out the six basic optimizations.
59. What
is meant by RAS and CAS in DRAM?
60. If
a 15% reduction in voltage leads to 15% reduction in frequency , what would be
the impact on dynamic energy and power?
61. What
is reorder buffer?
62. What
is meant by delayed branching?
63. Use GCD
test to identify if loop-carried dependency exists for the following loop:
for (i=1;i<=100;i++){
A[3*i+8]=A[3*i+2];
}
PART- B
1. How vector processor
works? Explain with an example.
2.
Explain in detail about SIMD
Instruction Set Extensions for Multimedia
3
Explain the concept of GPU and its instruction set architecture in
detail
4.
Detect and enhance the loop level parallelism with examples
5.
Explain the basic concepts of Thread level parallelism and explain in
detail about centralized shared Memory architectures with neat diagram
6.
Explain the basic concepts of Thread
level parallelism and explain in detail about Distributed shared Memory
architectures with neat diagram
7. Explain the Performance and Energy
Efficiency of the Intel Core i7 Multicore and explain the models of memory
consistency
8.
Compare SMT and CMP processors and explain in detail about
synchronization
9.
Explain the Compiler optimization to reduce the Miss Rate and reducing
cache miss penalty
10. Explain various levels of RAID and
concept of SRAM with neat diagrams
11. Explain the Hardware based
speculation
12. Discuss about the multithreading.
13. Explain the limitations of ILP.
14. Draw and Explain the vector
architecture
15. Discuss the performance evaluation
method of different computers
16. Discuss about the Instruction Set
Architecture
17. Explain the fundamentals of computer
design
18. Explain the trends in technology
19. Write short notes on energy and
power consumption in a Microprocessor
20. Explain the compilation techniques
that can be used to expose ILP
21. Explain in detail about cost, price
and their trends
22. What is dynamic scheduling? Explain
with suitable Examples the Tomasulo algorithm for MIPS processor
23. Explain the snoop based cache
coherence protocol with a state diagram
24. Explain in detail about Dynamic
branch prediction with Suitable examples
25. Explain the types of dependencies in
ILP
26. Explain (a) Multithreading (b)
Hardware Speculation
27. Discuss the salient features of
vector processors
28. Discuss the salient features of the
intel i7 processor
29.
Discuss similarities and differences between Vector architecture and GPU’s
30.
Suppose that in 1000 memory references there are 40 misses in the first-level
cache and 20 misses in the second-level cache. What are the various miss rates?
Assume the miss penalty from the L2 cache to memory is 200 clock cycles, the
hit time of the L2 cache is 10 clock cycles, the hit time of L1 is 1 clock
cycle, and there are 1.5 memory references per instruction. What is the average
memory access time and average stall cycles per instruction?
31. Describe Distributed shared memory
Architecture in detail
32. Write
a short note on the different types of multiple issue processors
33. Explain detecting and enhancing Loop
level parallelism in detail
34. Discuss
and design issues in SMT and CMP Architecture
35. Explain the
categories of misses and how will you reduce cache miss rate
36. Briefly
describe about various raid levels with diagram
37. List and
explain various I/O performance measures
